CMOS (complementary metal oxide semiconductor) circuits are widely used in many applications, e.g., portable computers and cellular telephones. CMOS, due to very low power consumption and dissipation as well minimization of the current in the “off” state, is a very effective device configuration for implementing digital functions.
In implementation, CMOS semiconductors comprise both n-channel and p-channel MOS field effect transistors (MOSFETs). Further, within these CMOS structures, parasitic current paths exist associated by so-called parasitic bipolar transistors, which, under normal conditions, are not activated. However, when the parasitic pnp and npn bipolar transistors are activated, CMOS latch-up can occur. Activation can be initiated by voltage or current perturbations, or ionizing radiation. CMOS latch-up can also occur when regenerative feedback occurs between the npn and pnp parasitic bipolar transistors.
Various CMOS designs have been conceived to prevent CMOS latch-up. For example, it is known to increase the spacing between devices which, in turn, increases the effective base width of the parasitic transistors. As should be understood, with such a design, the bipolar current gain will decrease as the base width increases. Thus, in such a design, as the N-diffusion moves away from the N-well, or the P-diffusion moves away from the N-well edge, or vertically, CMOS latch-up is less likely to occur.
Another approach to reducing CMOS latch-up sensitivity has been to increase doping concentrations. For example, by increasing the doping concentrations, the minority carrier lifetime is decreased; when the doping is in the base region, the bipolar current gain decreases. In a further design, isolation structures, such as shallow trench isolation (STI), have been provided to reduce the CMOS latch-up sensitivity.
As technology scales, however, the spacing between the P+ diffusion and the N-well and the N+ diffusion and N-well spacing is becoming smaller. Due to this scaling, the previous techniques to prevent CMOS latch-up are becoming more problematic. For example, it is more difficult to increase the doping in specific areas, since the increase in dopants will increase the out-diffusion of the dopants which, in turn, increases the capacitance of the device (at the junctions) impacting circuit performance. Also, as for shallow trench isolation (STI) structures, P+ to N+ space is scaled to maintain the aspect ratio of the isolation; hence the shallow trench isolation (STI) structure becomes shallower every generation, not deeper.